The present invention relates to a semiconductor memory device. More particularly, it relates to techniques which are effective when utilized for, e. g., the word line selector circuit of a CMOS static RAM (random access memory).
In a semiconductor memory device, with increase in the storage capacity thereof, a larger number of memory cells are coupled to each word line. Consequently, when one word line has been selected, data is neither read nor written from/into an increased number of memory cells, and the current consumption of the select operation increases. Therefore, for lowering such a consumptive current and for decreasing the number of memory cells to be coupled to each word line, so as to quicken the operation of selecting the word line, it has been known that each word line to which memory cells are coupled is divided as shown in FIG. 6. That is, a main word line MWL is provided with divided word lines WL. Static RAMs furnished with such divided word lines are described in, for example, the official gazette of Japanese Patent Application Laid-open No. 72699/1984 and the official gazette of Japanese Patent Application Laid-open No. 72695/1984.